Emitter Coupled Logic (emitter coupled logic) belongs to the family of MSI circuits implemented with bipolar technology, is the most fastest available in the circuits of type MSI.
History:
Doors with ECL designs have been implemented even with vacuum tubes, and of course with discrete transistors. And the first family with ECL design, the ECL I, appeared in 62 with the first family of integrated circuits. Even at that time the family was faster (a typical propagation delay of 8ns.), And was already the most dissipated.
Today it may seem that much when 8ns CMOS circuits that consume very low (mostly static) far outweigh this benefit, but in reality the ECL technology has also evolved in design and manufacture, and currently get the ns delays significantly lower, with heavy drinking but not exorbitant.
Introduction:
Despite its limited use, this is one of the most rooted logic families, and noble ancestry, in digital technologies. You could even say that in general electronics, because the differential pair, in which the family is based, largely dominates analog integrated circuits. Bipolar family
As it is, the noise margin is not good. In this case not only reduced low margin, but also the margin at high level. This is a consequence of reduced trip logic. And the reason is that for speed should vary little voltage values.
The guiding principle of the family is trying to avoid at all costs that make up the circuit transistors enter saturation. As the switches are between court (or almost cut) and driving. Therefore we will always have driving transistors, so that consumption is continuous. Ie not only are current peaks in the transitions, but we always have a significant consumption in the circuit. On the other hand, the presence of significant currents in the circuit at all times, makes the fan-out is good.
is the fastest form of logic, since the active devices manage to work out of saturation. Also becomes even more making quick changes are even less logical signal (Dt = 800mV), that makes the time for loading and unloading of cargo and parasitic C are even lower ...
ECL circuit is based on the use of a current direction switch, which can be constructed with a differential pair that is polarized with a voltage and current Vr I cte both. the differential nature of the circuit makes it less susceptible to pick up noise.
There are 2 known forms, the ECL and ECL 10K 100k, the 100k is faster but consumes more power.
Structure:
ECL structure is based on a differential pair (Q1-Q2 and Q3) in which a branch is connected to a reference voltage, which determines the threshold HI / LO and another branch with n transistors in parallel to the n inputs. Differential can be obtained simultaneously two with the departure and negated output and very low jitter between them. These outputs are, finally, to respective emitter follower to provide current income and fan-out right, which in many cases can be fed directly 50Ω lines. It is common to have separate power pins for the latter transistors because, unlike the differential pair, the current varies with the signal if the two transistors are not connected to impedances equal. Feeding separately prevents these changes reach the differential pair.
This structure produces output simultaneously OR / NOR: any high level input causes the Q5 emitter pass high level and high level of Q6. By comparison, the structure function only produces TTL NAND.
Unlike other technologies (TTL, NMOS, CMOS), the ECL is supplied to the positive (Vcc) connected to ground, with the power between 0 and -5 '2 V, usually. Some families allow sea-5V VEE, to share food with TTL circuits.
Applications:
addition to the ECL logic families I, II ECL, ECL III and ECL100K ECL10K, ECL technology has been used in LSI circuits: Logic Arrays
Reports ( Motorola, Fairchild)
Microprocessors (Motorola, Ferranti F100)
To improve the performance of CMOS technology, the ECL is incorporated in certain critical functions in CMOS circuits, increasing speed while maintaining low total consumption.
Yoseph 18257871 ESS SECTION 2 CI BUITRAGO
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